Matlab HDL Code Generation and Verification Assignment help

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Topics for HDL Code Generation and verification  

• Preparing Simulink Models for HDL Code Generation, Generating: HDL code & test bench, generated HDL code with an HDL simulator, Interfacing external HDL code, Interfacing vendor party IP.
• Preparing a multirate model for generating HDL code, Generating HDL code with single clock pins, multiple clock pins, speed optimizations, area optimizations, hardware description languages, VHDL fundamentals.
• behavioral model, structural models, syntax , basic rules, design entry, behavioral simulation, logic synthesis , synthesizeable code development, design mapping to standard cells , field programmable gate array.
•  FPGA or ASIC implementation, Perform design iterations, target-independent VHDL or Verilog code for FPGAs and ASICs.
• Generating HDL code and testbench for a compatible Simulink model, Performing speed and area optimizations, Integrating handwritten code and existing IP, Verifying generated HDL code using testbench and cosimulation and HDL simulator, Synthesizing the generated HDL code using a HDL synthesis tool, Documenting and Tracing HDL Code, HDL Coding Standard.